esphome
FeaturedESPHome device configuration, firmware, and IoT product development. Covers ESP32, ESP32-S3, ESP32-C3, ESP32-C6, ESP32-H2, ESP32-P4, ESP8266, RP2040, RP2350, nRF52, LibreTiny, Shelly, Sonoff, Tuya, BLE proxy, Matter firmware, Thread, Zigbee, GPIO, sensor YAML, LVGL displays, LED strips, voice assistant hardware, device flashing, Arduino conversion, alarm_control_panel, lock, valve, media_player, microphone, speaker, audio DAC, event entities, datetime entities, Z-Wave proxy, MIPI DSI displays, and DLMS smart meters. Also covers designing new ESPHome-based products: hardware selection, component sourcing, PCB design (KiCad), enclosures, 3D printing, CE/FCC certification, BOM optimization, and manufacturing from prototype to production scale.
Install
Quality Score: 88/100
Skill Content
Details
- Author
- tonylofgren
- Repository
- tonylofgren/aurora-smart-home
- Created
- 8 months ago
- Last Updated
- 6 days ago
- Language
- Python
- License
- MIT
Integrates with
Bundled in these plugins
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Chip-level ESP-IDF capability reference for the ESP32-S3 SoC (Xtensa LX7 dual-core) — what the chip can do, distinct from any board's wiring. Use when a user wants to go beyond basic Arduino sketches and exploit ESP32-S3 hardware — RMT (IR/WS2812/custom protocols), LEDC (PWM), I2S (audio), ADC/touch sensing, PCNT (encoders), MCPWM (motor control), TWAI/CAN, SDMMC/SD-SPI, native USB OTG vs the USB-Serial-JTAG controller, sleep modes and wake sources, ULP-FSM/ULP-RISC-V coprocessors, octal/quad PSRAM config, dual-core FreeRTOS task pinning and IRAM/ISR placement, WiFi/BLE coexistence, and the SIMD instructions behind esp-dsp/ESP-DL/TFLite Micro. Trigger on "how do I use RMT/LEDC/I2S/ULP/deep sleep/dual core/PSRAM/USB OTG on an ESP32-S3", low-power/performance-tuned S3 firmware questions, or any M5Stack S3 board (Cardputer, Cardputer Adv, AtomS3, AtomS3R, CoreS3, StickS3, Stamp-S3) needing depth beyond its own SKILL.md. For pinouts/wiring use that board's skill — this is the shared chip layer it points into.
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Plans and orchestrates a complete ESPHome device or fleet result from a requirement, so the user never has to pick which ESPHome skill produces what. Decomposes it into the minimal dependency-ordered set of artifacts across the ha-esphome-* family — repository layout and packages, the device file, sensors and buses, Home-Assistant-driven bindings, display content, the voice satellite, CI validation — presents that plan for approval, then dispatches the owning skills resolved from the live inventory at runtime, threading device identities, package parameters, and entity ids between steps. Generation only: it never compiles, flashes, or rolls out, and never runs the review itself — the read-only reviewer agents stay a separately triggered pass, so an artifact is never judged by its own author. Activate on "build me an ESPHome device for…", "set up my ESPHome fleet", or equivalent German requests. Do not activate for a single clear artifact (the owning skill). Supports resume.
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Chip-level ESP-IDF capability reference for the classic ESP32 SoC (dual-core Xtensa LX6) — what the chip can do, distinct from board wiring. Covers the ESP32-D0WDQ6-V3 / ESP32-D0WD-V3 / ESP32-D0WDR2-V3 die family used in ESP32-WROOM-32 and ESP32-WROVER modules. Use for RMT (IR/WS2812), LEDC (PWM), I2S (audio/parallel camera), ADC/DAC/touch (incl. ADC2-vs-WiFi conflict), PCNT, MCPWM, TWAI/CAN, SDMMC host + SDIO slave, the deprecated Hall sensor, ULP-FSM, deep sleep/hibernation, dual-core task pinning, WiFi/Bluetooth Classic+BLE coexistence, and what "V3" silicon changed vs older revisions. Trigger on RMT/LEDC/I2S/ULP/deep-sleep/ADC2 questions on a classic ESP32, D0WDQ6/D0WD/D0WDR2/WROOM/WROVER, or any M5Stack classic-ESP32 board (Core2, Basic, Fire, Tough, StickC-Plus, Atom-Lite/Matrix, Stamp-Pico, CoreInk, Paper) needing depth beyond its own SKILL.md. For pinouts/wiring use that board's skill — this is the shared chip layer it points into.