esp32listed

# ESP32 (classic) chip capabilities This skill is the **chip layer**, not a board layer. A board skill (e.g. `m5stack-core2`) tells you what's wired to what on one specific product; this skill tells you what the classic ESP32 silicon itself can do — the peripherals, low-power modes, memory options, and concurrency model that are the same on every classic-ESP32 board regardless of vendor. Read a board's own skill first for pin numbers and I2C addresses, then come here when the user wants to go deeper on a capability than "call the vendor's high-level library and move on" — e.g. writing a custom RMT-based protocol, understanding why an ADC read returns garbage once WiFi turns on, tuning deep-sleep/hibernation wake behavior, or pinning tasks to cores. ## What "ESP32-D0WDQ6-V3" actually names This is the oldest and most fragmented naming scheme in the family, worth untangling explicitly: - **D0WD / D0WDQ6 / D0WDR2** identify the *die + package*, not a firmware target — all three are the same dual-core Xtensa LX6 silicon, differing only in package size and whether flash/PSRAM is bonded into the same package: - **ESP32-D0WD-V3** — QFN 5×5mm, no in-package flash or PSRAM (external only). - **ESP32-D0WDQ6-V3** — QFN 6×6mm (larger, more pins broken out for external QSPI), no in-package flash or PSRAM (external only). This is the die used inside **ESP32-WROOM-32** modules, which add the external flash chip inside the module's own metal can — the bare D0WDQ