assembly-riscv

# RISC-V assembly RISC-V is a small load-store ISA grown through named extensions. This skill covers user-mode RV32 and RV64 assembly, the psABI register contract, and the QEMU loop. ## Contract | Field | Bound contract | |---|---| | Trigger | The task writes inline asm or assembly for RV32 or RV64, decodes ABI register names, names an ISA extension string, enables compressed instructions, or debugs RISC-V under QEMU with GDB. | | Authority | Read-only. The skill explains and drafts; edits land through the normal coding path. No remote mutation. | | Side effect | None. | | Done | The drafted assembly assembles for the named base ISA and extensions, or the compiler output under discussion is explained register by register. | ## Inputs - The C or C++ source, assembly fragment, or compiler output: required. - The base ISA and extensions: required. The `-march` string such as `rv64gc`, written `IMAFDC` in ISA order. - The execution environment: required. QEMU `virt` for user or system work, hardware otherwise. ## Procedure 1. Map registers by role. The ABI names are what disassembly and assembly listings show. Done when: every register in the fragment is classified. | Register | ABI name | Role | |----------|----------|------| | `x0` | `zero` | Hardwired zero, writes are discarded | | `x1` | `ra` | Return address | | `x2` | `sp` | Stack pointer | | `x3` | `gp` | Global pointer | | `x4` | `tp` | Thread pointer | | `x5` to `x7`, `x28` to `x31` | `t0` to `t6` | Temporaries, ...