freemodbus-integration
SolidUse when integrating, porting, configuring, or debugging FreeModbus RTU, ASCII, TCP, serial ports, timers, events, register callbacks, or Modbus protocol issues
AI & Automation 22 stars
2 forks Updated 1 weeks ago MIT
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Skill Content
# FreeModbus Integration
## Overview
Use this skill to integrate FreeModbus by proving the port layer first: serial/TCP transport, timing, event dispatch, and register callbacks. Modbus bugs are often timing, endian, addressing, or task-context problems rather than protocol logic.
## When To Use
Use this skill when:
- The user wants to add or debug FreeModbus RTU, ASCII, or TCP.
- The issue involves `portserial.c`, `porttimer.c`, `portevent.c`, register callbacks, CRC errors, timeouts, slave ID, function codes, or Modbus TCP/lwIP integration.
- A device does not respond, responds with exception codes, or has wrong register values.
Do not use this skill when the UART or network transport is not verified. Use serial or lwIP skills first if the lower layer is unknown.
## First Questions
Ask for:
- Mode: RTU, ASCII, TCP, master, slave, or gateway.
- MCU/RTOS/compiler and FreeModbus fork/version.
- Transport: UART/RS-485, TCP/lwIP, or custom.
- Baud, parity, stop bits, DE/RE control, slave ID, and timeout settings.
- Register map and callback code.
- Logic analyzer, serial capture, Modbus poll output, or exception codes.
## Integration Checklist
1. Prove transport timing.
For RTU, verify baud, parity, stop bits, inter-frame gap, and RS-485 direction control.
1. Implement port files.
Serial, timer, and event callbacks must match the target scheduler and ISR rules.
1. Confirm protocol mode.
RTU, ASCII, and TCP have different framing, timing, and porting require...
Details
- Author
- easyzoom
- Repository
- easyzoom/aix-skills
- Created
- 3 months ago
- Last Updated
- 1 weeks ago
- Language
- Python
- License
- MIT
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