chip-design-flowlisted

Use when guiding RTL-to-GDSII chip design flow including RTL coding style, synthesis constraints, place-and-route strategy, timing closure, and tape-out checklist. Do not use for verification methodology (use verification-methodology) or SoC integration (use soc-integration).
dtsong/my-claude-setup · ★ 5 · AI & Automation · score 76

Install: claude install-skill dtsong/my-claude-setup

# Chip Design Flow ## Purpose Guide the end-to-end RTL-to-GDSII design flow, ensuring clean synthesizable RTL, realistic constraints, timing closure, and tape-out readiness. ## Scope Constraints Reviews RTL source, constraint files, and EDA tool reports. Does not execute EDA tools or modify design files. Does not perform physical verification (LVS/DRC) directly. ## Inputs - RTL source files or design specification - Target technology node and foundry PDK - Performance targets (clock frequency, area budget, power budget) - Existing SDC constraints and floor plan, if any ## Input Sanitization No user-provided values are used in commands or file paths. All inputs are treated as read-only analysis targets. ## Procedure ### Progress Checklist - [ ] Step 1: Review RTL coding style - [ ] Step 2: Define synthesis constraints - [ ] Step 3: Plan floor plan and power strategy - [ ] Step 4: Guide place-and-route - [ ] Step 5: Achieve timing closure - [ ] Step 6: Tape-out readiness checklist ### Step 1: Review RTL Coding Style - Verify all RTL is synthesizable (no `initial`, `#delay`, `force` in design code). - Check clock domain crossing (CDC) handling with proper synchronizers. - Verify reset strategy (async vs sync, reset tree planning). - Flag combinational loops and unintended latches. - Confirm coding style matches foundry library expectations (e.g., no tri-state in core logic). ### Step 2: Define Synthesis Constraints - Write SDC constraints: clock definitions, genera