arm-aarch64-exception-levels-memory-model-and-mmulisted

# ARM: AArch64, Instruction Set Characteristics, Exception Levels, the Memory Model, and MMU and Translation > **Part 2 of 6** of the *ARM: A Deep Dive* reference (plugin `arm-architecture-deep-dive`), covering §5–§9. Sibling skills: `arm-what-arm-is-licensing-families-and-isa-generations` (§0–§4), `arm-vectors-atomics-numerics-and-security-architecture` (§10–§15), `arm-system-architecture-boot-and-virtualization` (§16–§20), `arm-cortex-m-toolchain-porting-and-performance` (§21–§25), `arm-reference` (§26–§31). Section numbers are shared across the set; a reference written as §N → `skill` points into that sibling skill. > > **Currency:** The architecture is documented and stable. Two things moved decisively. See §26 → `arm-reference` for Arm's business model, and its actual market position. > **⚠️ ARM is a business model as much as an instruction set, and you cannot understand the > architecture without understanding that.** ⚠️ **The design choices — modularity, optional > extensions, profiles, strict architectural compliance — exist because the ISA has to be > implementable by dozens of independent companies at wildly different power and > performance points.** > > **Builds on a microarchitecture reference (§20 ISA design, §8 memory consistency) and a > semiconductor reference. Complements a digital-logic reference for the boot chain and a > computer-hardware reference for the datacentre context.** > > **⚠️ GOTCHA** boxes mark where ARM differs from x86 in ways that break a