timing-constraints

# Timing Constraints Skill Expert skill for FPGA timing constraint development following SDC (Synopsys Design Constraints) and Xilinx XDC standards. Provides deep expertise in clock definition, I/O timing, false paths, multicycle paths, and constraint validation. ## Overview The Timing Constraints skill enables comprehensive timing constraint development for FPGA designs, supporting: - Clock definition (create_clock, create_generated_clock) - Input/output delay constraints - False path identification and specification - Multicycle path constraints with setup/hold - Clock groups and relationships - Constraint coverage validation - Vendor-specific XDC extensions ## Capabilities ### 1. Primary Clock Definition Define primary clocks entering the FPGA: ```tcl # Primary clock on input pin create_clock -name sys_clk -period 10.000 [get_ports clk_100mhz] # Clock with duty cycle specification create_clock -name sys_clk -period 10.000 -waveform {0 5} [get_ports clk_100mhz] # Multiple primary clocks create_clock -name clk_a -period 8.000 [get_ports clk_125mhz] create_clock -name clk_b -period 6.667 [get_ports clk_150mhz] # Clock on GT/transceiver reference create_clock -name gt_refclk -period 6.400 [get_ports gt_refclk_p] # Virtual clock (for I/O timing without physical pin) create_clock -name virt_clk -period 10.000 ``` ### 2. Generated Clock Definition Define clocks derived from primary clocks: ```tcl # MMCM/PLL output clocks (auto-derived in Vivado) create_generated_clo...