tapeout-prechecklisted

# Tapeout Precheck ## Overview Tapeout is irreversible and expensive. The precheck is the last gate where a tool, not a person, confirms the layout obeys the foundry rules and matches the schematic. The job is to pass that gate honestly, because the alternative is paying for a respin to learn what the checker already knew. **Core principle:** A physical-verification failure is the design telling you it's wrong. Fix the design, never the checker. Every disabled rule is a defect you chose to ship. ## When to Use - Preparing a GDS for an MPW shuttle or full-mask submission - Running DRC (design rule check) or LVS (layout vs schematic) signoff - Packaging the submission (GDS, top-cell name, layer map, fill, metadata) - Tempted to wave, downgrade, or disable a DRC/LVS violation to make a deadline ## The Signoff Gate, In Order 1. **DRC clean.** Geometry obeys the foundry rules (spacing, width, density, antenna, latchup). Zero unwaived violations. 2. **LVS clean.** The extracted layout netlist matches the schematic/source netlist exactly: same devices, same connectivity, no shorts, no opens, no unintended merges. 3. **Density / fill.** Metal density windows satisfied, fill added without creating new violations. 4. **Submission package.** Correct top-cell name, layer mapping, and the foundry's required metadata and file format. A perfect GDS rejected for a wrong top-cell name is a wasted shuttle slot. A precheck step may be a no-op for a given flow (some shuttles run DRC on t