fpga-synthesis-fitlisted

# FPGA Synthesis and Fit ## Overview Getting RTL to fit and route on an FPGA is a measurement problem before it is an optimization problem. The tools report several different "area" numbers and most of them lie about what will actually fit. Optimizing against the wrong number burns hours and can make the real result worse. **Core principle:** Judge fit and timing by the post-pack, post-place numbers (nextpnr `TRELLIS_COMB` and the critical-path report), never by the synthesis-stage estimate. Measure with data before you change RTL. ## When to Use - Synthesizing with yosys + nextpnr (ECP5/prjtrellis or a similar open flow) - A design won't fit, or the router thrashes and never converges - Measuring Fmax or per-module area - Building a ROM/RAM and unsure whether it became block RAM or flops - Generating a bring-up bitstream and picking its clock ## The Metric Trap: Pre-Pack LUT4 != Post-Pack TRELLIS_COMB yosys `stat` after `synth_ecp5` reports `LUT4`, which is pre-pack. nextpnr reports `TRELLIS_COMB`, which is post-pack (LUT4 plus PFUMX, L6MUX21, and carry packed into slices). These differ, sometimes a lot. A change that cuts `LUT4` can be neutral or worse for `TRELLIS_COMB`. Replacing a barrel shifter with a mux tree is the classic example: barrel shifters pack densely into carry chains, mux trees spread into PFUMX/L6MUX. Always judge by the nextpnr `Device utilisation: TRELLIS_COMB` line. An 80% pre-pack can be a 91% post-pack that won't route. ## Routing Congestion: