fpga-bringuplisted

# FPGA Bring-Up ## Overview Bringing up an FPGA on the bench means three things: get the bitstream in over a real transport, drive the design's inputs, and observe its outputs. Most early failures are transport and pin-mapping problems, not logic problems. **Core principle:** Bring the transport up first and prove it independently, before you trust anything the design does. A bitstream that "loaded" but didn't is the most expensive hour on the bench. ## When to Use - Loading a bitstream onto a board over JTAG, SPI, or a custom config chain - Bit-banging JTAG from GPIO (Pi-as-host, no FTDI/FT2232) - Driving test vectors into pins and reading results back - Configuration "succeeds" but the design doesn't run ## Bring Up The Transport First Before any design-level work, prove the link end to end: 1. **Read the IDCODE.** Shift the JTAG IDCODE instruction and confirm the value matches the part. If IDCODE is wrong or all-ones/all-zeros, you have a wiring, voltage, or clock problem. Stop here and fix it. Nothing downstream matters yet. 2. **Confirm the IR width.** The instruction register width is part-specific and must match the design's TAP. A wrong IR width shifts every instruction into garbage and configuration silently no-ops. Make the IR width a parameter, not a magic constant baked in one place. 3. **Confirm clock and levels.** TCK speed, signal voltage, pull directions. Bit-banged GPIO has no buffering; mind the levels and keep TCK slow until the link is proven. ##