bscost-netlisted

# BS Cost Net Use this skill to move model work from single-design intuition to reproducible, multi-design evidence. ## Step 1: Scope and objective lock Define objective before tuning: 1. `Primary`: model is more stable than HPWL across designs/seeds. 2. `Secondary`: model improves correlation/sign behavior in key buckets (long/high-fanout clock-like nets). 3. `No-claim`: do not claim superiority from one design only. 4. Run preflight reflection first (`eda-preflight-reflect`) and capture current failure shape before designing next batch. ## Step 2: Internet-backed benchmark selection Use network research with primary sources only: 1. Confirm candidate open-source CPU/accelerator repos and status. 2. Build benchmark set beyond systolic-array-only. 3. Record selected commit/release identifiers in experiment notes. Minimum baseline set: 1. `systolic_array_*` (continuity with existing results) 2. `rocket-chip` class SoC design 3. `gemmini` class accelerator design Load: - `references/benchmark_candidates.md` - `references/web_research_protocol.md` ## Step 3: Model construction plan Build two model tracks: 1. Backside signal-net cost model. 2. Backside clock-net cost model. For theory-grounded fitting and promotion gates, pair with: 1. `bscost-theory-opt` For both tracks, keep output fields aligned: 1. `cost_front`, `cost_back`, `delta_cost`, `min_cost` 2. target delay fields with fixed sign contract 3. bucket tags (length, fanout, TSV-proxy) Load: - `references/model_pl